Asynchronous Communication Circuits: Design, Test and Synthesis

This thesis presents the design and testing of asynchronous communication mechanism (ACM) circuits, and the development of an asynchronous circuit synthesis method which not only supports the ACM work but also has much wider application potential. ACMs are a unique approach to data transmission between subsystems not synchronized with one another. The successful systematic implementation of ACM hardware circuits presented here demonstrates the potential of ACM applications in hardware systems and establishes a number of techniques well suited for ACM hardware design and synthesis. Novel testing procedures are developed specially for ACM circuits, and testing carried out on fabricated ACM circuits complement knowledge on the ACM implementations gained from analyses and simulations. The asynchronous circuit synthesis method proposed in this thesis and its useful library proved to be very helpful in bringing an element of automation to the design and implementation process. Not limited to ACM circuits, this method can be further developed to help designers of general asynchronous circuits. NCL-EECE-MSD-TR-2003-100 Asynchronous (or self-timed) circuits and systems have attracted increasing attention from the research community in recent years. The inherent concurrency in their operation and the absence of the requirement for a pre-determined settling period, the clock cycle, means that these systems reflect more naturally the processes happening in real life. 1.1.1 General purpose motivation Most digital circuits designed and fabricated today are “synchronous”. In essence, they are based on two fundamental assumptions that greatly simplify their design: 1. all signals are binary and; 2. all components share a common and discrete notion of time, as defined by a clock signal distributed throughout the circuit. By making the assumption of a synchronous mode of operation, designers can abstract from the problem of tracking of all intermediate states of the system. It can be safely assumed that the clock period is chosen to be long enough for the signals to settle to their new values. Any feedback is cut off to prevent the changing outputs Chapter 1: Introduction